Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : Design Verification Testing
Good to have skills : NA
Minimum 7.5 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive test environments to ensure the accuracy and reliability of digital designs. This role requires close collaboration with various teams to identify potential edge cases and verify that all functional aspects of the design are thoroughly tested. The engineer focuses on creating diverse testing scenarios and analyzing results to guarantee the design meets all specifications before final production stages. Continuous communication and coordination with design and architecture teams are essential to maintain alignment and address any issues promptly throughout the verification process.
Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage.
- Mentor junior team members to support their professional growth and skill development.
- Coordinate cross-functional reviews to ensure alignment on verification goals and deliverables.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design Verification Testing.
- Strong knowledge of verification methodologies including constrained-random testing, directed testing, and coverage-driven verification.
- Experience with hardware description and verification languages such as SystemVerilog and Universal Verification Methodology.
- Ability to develop and maintain complex testbenches for block and system level verification.
- Familiarity with debugging tools and simulation environments to analyze and resolve functional issues.
- Skilled in collaborating with design and architecture teams to identify and cover corner cases effectively.
Additional Information:
- The candidate should have minimum 7.5 years of experience in Design Verification Testing.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.
Bengaluru
平等就业机会声明
所有聘用决定均不考虑年龄、种族、信仰、肤色、宗教、性别、国籍、血统、残疾状况、退伍军人身份、性取向、性别认同或表达、基因信息、婚姻状况、公民身份或任何其他受联邦、州或地方法律保护的因素。
求职者在招聘过程中没有义务披露已封存或已删除的定罪或逮捕记录。
埃森哲致力于为我们的男女军人提供退伍军人就业机会。
请阅读埃森哲的招聘和聘用声明，了解更多关于我们在招聘和聘用过程中如何处理您的数据的信息。
We work with one shared purpose: to deliver on the promise of technology and human ingenuity. Every day, more than 775,000 of us help our stakeholders continuously reinvent. Together, we drive positive change and deliver value to our clients, partners, shareholders, communities, and each other.
We believe that delivering value requires innovation, and innovation thrives in an inclusive and diverse environment. We actively foster a workplace free from bias, where everyone feels a sense of belonging and is respected and empowered to do their best work.
At Accenture, we see well-being holistically, supporting our people’s physical, mental, and financial health. We also provide opportunities to keep skills relevant through certifications, learning, and diverse work experiences. We’re proud to be consistently recognized as one of the World’s Best Workplaces™.
Join Accenture to work at the heart of change. Visit us at www.accenture.com.